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| SSM9972GP,S N-CHANNEL ENHANCEMENT-MODE POWER MOSFET Low gate-charge Simple drive requirement Fast switching G D BV DSS R DS(ON) ID 60V 18m 60A S Description The SSM9972GS is in a TO-263 package, which is widely used for commercial and industrial surface mount applications, and is well suited for low voltage applications such as DC/DC converters. The through-hole version, the SSM9972GP in TO-220, is available for low-footprint vertical mounting. These devices are manufactured with an advanced process, providing improved on-resistance and switching performance. G GD S TO-263 (S) Pb-free lead finish (second-level interconnect) D TO-220(P) S Absolute Maximum Ratings Symbol VDS VGS ID @ TC=25C ID @ TC=100C IDM PD @ TC=25C Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current 1 3 Rating 60 25 60 38 230 89 0.7 Units V V A A A W W/C Total Power Dissipation Linear Derating Factor TSTG TJ Storage Temperature Range Operating Junction Temperature Range -55 to 150 -55 to 150 C C Thermal Data Symbol Rthj-c Rthj-a Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max. Max. Value 1.4 62 Units C/W C/W 2/16/2005 Rev.1.1 www.SiliconStandard.com 1 of 5 SSM9972GP,S Electrical Characteristics @ T j=25oC (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage 2 Test Conditions VGS=0V, ID=250uA Min. 60 1 - Typ. 0.06 55 32 8 20 11 58 45 80 280 230 1.7 Max. Units 18 22 3 10 25 100 51 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/ Tj RDS(ON) Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA Static Drain-Source On-Resistance VGS=10V, ID=35A VGS=4.5V, ID=25A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Rg Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=150oC) o VDS=VGS, ID=250uA VDS=10V, ID=35A VDS=60V, VGS=0V VDS=48V ,VGS=0V VGS=25V ID=35A VDS=48V VGS=4.5V VDS=30V ID=35A RG=3.3,VGS=10V RD=0.86 VGS=0V VDS=25V f=1.0MHz f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance 2 3170 5070 Source-Drain Diode Symbol VSD Parameter Forward On Voltage 2 Test Conditions IS=35A, VGS=0V IS=35A, VGS=0V, dI/dt=100A/s Min. - Typ. 50 48 Max. Units 1.2 V ns nC trr Qrr Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 2/16/2005 Rev.1.1 www.SiliconStandard.com 2 of 5 SSM9972GP,S 200 150 10V 7.0V ID , Drain Current (A) 150 10V 7.0V ID , Drain Current (A) 100 5.0V 100 5.0V 4.5V 4.5V 50 50 T C =25 C 0 0 2 4 6 8 10 o V G =3.0V T C = 150 C o V G =3.0V 0 12 14 0 2 4 6 8 10 12 14 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 20 1.6 I D = 25 A T C =25 o C 18 1.4 I D =35A V G =10V Normalized RDS(ON) 2 4 6 8 10 RDS(ON) (m ) 1.2 1.0 16 0.8 14 0.6 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 1.7 20 15 Normalized VGS(th) (V) T j =150 o C IS(A) 10 T j =25 o C 1.2 0.7 5 0 0 0.2 0.4 0.6 0.8 1 1.2 0.2 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( o C) Fig 5. Forward Characteristic offf Fig 6. Gate Threshold Voltage vs. Reverse Diode Junction Temperature 2/16/2005 Rev.1.1 www.SiliconStandard.com 3 of 5 SSM9972GP,S f=1.0MHz 12 10000 I D = 35 A VGS , Gate to Source Voltage (V) 10 8 V DS =48V V DS =38V V DS =30V C (pF) 1000 C iss 6 4 2 C oss C rss 0 0 20 40 60 100 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 1000 1 Normalized Thermal Response (R thjc) Duty factor=0.5 100 0.2 ID (A) 100us 1ms 10 0.1 0.1 0.05 PDM 0.02 10ms T C =25 C Single Pulse o t T 0.01 100ms DC 10 100 1000 Single Pulse Duty factor = t/T Peak Tj = PDM x Rthjc + TC 1 0.1 1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 10 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance 100 V DS =5V 80 VG T j =25 o C T j =150 o C ID , Drain Current (A) QG 4.5V 60 QGS 40 QGD 20 Charge 0 0 2 4 6 8 Q V GS , Gate-to-Source Voltage (V) Fig 11. Transfer Characteristics 2/16/2005 Rev.1.1 Fig 12. Gate Charge Waveform www.SiliconStandard.com 4 of 5 SSM9972GP,S Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 2/16/2005 Rev.1.1 www.SiliconStandard.com 5 of 5 |
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